airhdl Feature Requests
44 results found
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Option for synchronous reset of axi interface
To get the maximum performance, and smallest of a design the same type of reset should be used throughout the design, according to this document: https://www.xilinx.com/support/documentation/white_papers/wp275.pdf
This register generator currently uses asynchronous reset. It would be nice to have an option to use synchronous reset. If the reset of the design uses synchronous reset, all flip-flops would use the same type of reset and can be implemented directly into the flip-flop yielding better performance and are usage. Currently there is no way of changing the type of reset, which is unfortunate if used in a design that implements synchronous reset.
6 votes -
Add option to not generate strobe port
Sometimes the strobe port is not needed and generated unnecessary ports
Would be nice to have an option to not generate this port so in the sblock design the module will look nicer.5 votes -
Add option to split register arrays and still create one single array output
Add the ability to split register arrays up in equal parts and generate single array output.
Ex.
Register:
| [7:0] | [7:0] | [7:0] | [7:0] |Each element in the array would be 8 bits long instead of 32, but still be apart of the same array.
Current solution would generate 4 different array outputs.
1 vote -
Wrap records on a register basis
Be able to select registers to be wrapped in records. This will allow the user to select only the registers he want to use records. The rest will use regular signals.
1 vote -
Return magic value in case of read address miss
when reading from an unmapped address location, optionally return a magic value like 0xDEADBEEF instead of an AXI error.
1 vote -
Add support for additional register types
Ability to support the following register types:
- write-1-to-clear status "sticky" bits
- write pulse acknowledge. Similar to the write pulse, but stays asserted until hw sends the ack which then clears the bit.6 votes -
uvmreg generation
generate uvm register format
4 votesHi, thanks for suggesting this feature. Could you please send us an example of how file should look like?
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Support APB Interface
APB is used in Microsemi RISC-V designs.
5 votes -
Type cast registers
Ability to type cast registers i.e. signed or unsigned rather than stdlogicvector to be more descriptive.
2 votesThanks for the feedback!
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Add an option for a Wishbone bus interface instead of AXI
Support the Wishbone bus in addition to AXI. It's free & open IP, it's very easy to interface to, and an excellent fit for many applications that don't need the sophistication of AXI.
The more complex Wishbone features such as stalls, retires, pipelining etc. need not be supported for this to have a lot of value.6 votes -
Add AXI burst functionality to bus interface
The AXI interface in the generated files currently doesn't support burst transfer. Could be added with a parameter for maximum burst size.
6 votes -
Any size register width
We use register widths of 64 or 128 in a number of cases. It would be nice if Airhdl could generate multiples of 32 bit register widths.
40 votes -
Generate C code driver templates
Aiirhdl should also generate c code templates to read/write any register.Currently only generates a header file (base address)
9 votes -
Support User Clocks
Add a user-clock input port to the register component, and handle the bus <-> user clock domain crossings in the component.
27 votes -
Support Address Gaps
allow +register to start at the end of any address gap, showing existing gaps
1 vote -
Add an option to sort bit fields MSB:LSB
Add a configuration option to display register bit fields sorted high to low, instead of low-to-high as is done now.
The proposed option should affect both the editor and in the generated documentation.1 votethanks for suggesting this!
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Create a mobile version of airhdl
for use on smartphones or tablets
1 vote -
Move field to another register
Sometimes it's necessary to move a field from one register to another register.
Currently, the only way to do that is to delete the field from the source register and to re-create it from scratch in the target register.
It would be useful to have a function for that.
1 vote -
Add functions for setting/getting register field values
When writing testbenches, we often have to set/get the value of single fields within a variable representing the value of a register.
Currently, the only way to do that is to use the <register><field>BITOFFSET and <register><field>BITWIDTH from the VHDL/SV packages:
MemRegv(CTRLDURATIONBITWIDTH + CTRLDURATIONBITOFFSET - 1 downto CTRLDURATIONBITOFFSET) := "1000";
I would be nice to have a "setregisterfield" function for that, which could take the register and field names as arguments:
MemRegv := setregisterfield("CTRL", "DURATION", "1000", MemRegv);
2 votes -
Support of IPXACT 1685-2014 generation
For supporting the IP-XACT envrionment of the lastest version.
2 votes
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