Support User Clocks
Add a user-clock input port to the register component, and handle the bus <-> user clock domain crossings in the component.
27
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AdminGuy Eschemann
(Manager, airhdl)
shared this idea
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pswirhun commented
We have been putting Xilinx AXI clock converter blocks on the AXI side of a lot of register files, since we need the much larger number of data I/Os at the other side of the register file to be on a different clock domain than the AXI bus. Rather than synchronize every register value, we synchronize on the bus side. It would be great if there was a checkbox to basically make the AXI side asynchronous from the data side like this.