pswirhun
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40 votespswirhun
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We have been putting Xilinx AXI clock converter blocks on the AXI side of a lot of register files, since we need the much larger number of data I/Os at the other side of the register file to be on a different clock domain than the AXI bus. Rather than synchronize every register value, we synchronize on the bus side. It would be great if there was a checkbox to basically make the AXI side asynchronous from the data side like this.
pswirhun
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5 votespswirhun
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AirHDL should at least support 32/64/128-bit wide AXI data ports, and interfaces to registers and memory that have 64-bit wide data.
These three widths are data port widths of AXI master/slave interfaces that are supported on Zynq devices such as XCZUxxxx. The PS is often a 64-bit Cortex-A53, so at the very least it would make sense that you should support 64-bit wide data. Furthermore, it is common to read and write to 64-bit BRAMs or URAMs running in 64/72-bit mode with hardware ECC included for SECDED in Ultrascale/Ultrascale+ devices. To read or write from these memories, we need AirHDL to support 64-bit AXI data paths and 64-bit data ports on the generated memory interfaces.