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  1. Add register input/output pipeline option using generic

    4 votes
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    1 comment  ·  airhdl Feature Requests  ·  Admin →
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    Guillaume shared this idea  · 

  2. Add support for additional register types

    6 votes
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    under review  ·  2 comments  ·  airhdl Feature Requests  ·  Admin →
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    Guillaume commented  · 

    Hello Guy,

    I really need such feature too :)
    In our register map, we use self clearing register on Read ("RC" behavior below)

    -> That would be very useful to have all the standard UVM register behavior :
    https://github.com/accellera/uvm/blob/master/distrib/src/reg/uvm_reg_field.svh#L190
    // "RO" - W: no effect, R: no effect
    // "RW" - W: as-is, R: no effect
    // "RC" - W: no effect, R: clears all bits
    // "RS" - W: no effect, R: sets all bits
    // "WRC" - W: as-is, R: clears all bits
    // "WRS" - W: as-is, R: sets all bits
    // "WC" - W: clears all bits, R: no effect
    // "WS" - W: sets all bits, R: no effect
    // "WSRC" - W: sets all bits, R: clears all bits
    // "WCRS" - W: clears all bits, R: sets all bits
    // "W1C" - W: 1/0 clears/no effect on matching bit, R: no effect
    // "W1S" - W: 1/0 sets/no effect on matching bit, R: no effect
    // "W1T" - W: 1/0 toggles/no effect on matching bit, R: no effect
    // "W0C" - W: 1/0 no effect on/clears matching bit, R: no effect
    // "W0S" - W: 1/0 no effect on/sets matching bit, R: no effect
    // "W0T" - W: 1/0 no effect on/toggles matching bit, R: no effect
    // "W1SRC" - W: 1/0 sets/no effect on matching bit, R: clears all bits
    // "W1CRS" - W: 1/0 clears/no effect on matching bit, R: sets all bits
    // "W0SRC" - W: 1/0 no effect on/sets matching bit, R: clears all bits
    // "W0CRS" - W: 1/0 no effect on/clears matching bit, R: sets all bits
    // "WO" - W: as-is, R: error
    // "WOC" - W: clears all bits, R: error
    // "WOS" - W: sets all bits, R: error
    // "W1" - W: first one after ~HARD~ reset is as-is, other W have no effects, R: no effect
    // "WO1" - W: first one after ~HARD~ reset is as-is, other W have no effects, R: error

    Guillaume supported this idea  · 

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