Christian Lanius
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3 votes
Thanks for suggesting this feature. For further analysis, it would be very helpful if you could provide a concrete application example for this. Thanks, Guy.
An error occurred while saving the comment An error occurred while saving the comment Christian Lanius
commented
Dear Guy,
Thank you for taking your time to have a look at this. I do not want to burden you with any work.
Assume I have some custom memory, that takes many (possibly indeterminate number of) cycles to write. During that time, the address and data have to be constant. Note that the actual application that I have is too big to show here. I have written a minimum example gist here, where such an accept flag would be useful: https://gist.github.com/christian-lanius/2f321e363c21b9ef22f14e0b508feb96. Currently, the AXI master has to wait long enough with the next transaction that we can guarantee that the write has taken place, or we have to add a large enough FIFO in the user code to make sure that on average we are fast enough.
Similarly if the memory has a random delay to access, the currently supported fixed delay is not enough to handle that case.
Kind regards
ChristianChristian Lanius
shared this idea
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Dear Guy,
I received your answer per mail, but it somehow does not show up here. The proposed solution of using a write only plus an interrupt register does work, and if it was a conscious design decision to not allow the AXI bus to stall, I will work with such an approach. I see the advantage of being able to guarantee that the bus does not stall indefinitely.
For us the downside of that approach is that we need to generate at least 3 AXI requests (write, polling read from interrupt register, write to clear).
Kind regards
Christian