airhdl Feature Requests
44 results found
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Any size register width
We use register widths of 64 or 128 in a number of cases. It would be nice if Airhdl could generate multiples of 32 bit register widths.
40 votes -
Support User Clocks
Add a user-clock input port to the register component, and handle the bus <-> user clock domain crossings in the component.
27 votes -
Generate C code driver templates
Aiirhdl should also generate c code templates to read/write any register.Currently only generates a header file (base address)
9 votes -
Hierarchical register structure
Allow registers to be put in a directory type structure.
8 votes -
Add an option for a Wishbone bus interface instead of AXI
Support the Wishbone bus in addition to AXI. It's free & open IP, it's very easy to interface to, and an excellent fit for many applications that don't need the sophistication of AXI.
The more complex Wishbone features such as stalls, retires, pipelining etc. need not be supported for this to have a lot of value.6 votes -
Option for synchronous reset of axi interface
To get the maximum performance, and smallest of a design the same type of reset should be used throughout the design, according to this document: https://www.xilinx.com/support/documentation/white_papers/wp275.pdf
This register generator currently uses asynchronous reset. It would be nice to have an option to use synchronous reset. If the reset of the design uses synchronous reset, all flip-flops would use the same type of reset and can be implemented directly into the flip-flop yielding better performance and are usage. Currently there is no way of changing the type of reset, which is unfortunate if used in a design that implements synchronous reset.
6 votes -
Support bit-level RW access types
As is, access granularity is defined at the register level. However certain bits may require accessibility in ways that others may not. This is a recurring theme on many designs I have worked on.
I think it would be useful to specify for example, that Reg[7] is Read-only, while Reg[6] is Write-only, and Reg[5:0] is R/W.
6 votes -
Add support for additional register types
Ability to support the following register types:
- write-1-to-clear status "sticky" bits
- write pulse acknowledge. Similar to the write pulse, but stays asserted until hw sends the ack which then clears the bit.6 votes -
Import existing register maps
This is for the case where someone wants to import an existing register map (e.g. in IP-XACT format) to AirHDL.
6 votes -
Add AXI burst functionality to bus interface
The AXI interface in the generated files currently doesn't support burst transfer. Could be added with a parameter for maximum burst size.
6 votes -
Add a global download button
Add a download button to the Register Maps view to allow downloading several register maps (e.g. JSONs) at once.
5 votes -
Support APB Interface
APB is used in Microsemi RISC-V designs.
5 votes -
Add option to not generate strobe port
Sometimes the strobe port is not needed and generated unnecessary ports
Would be nice to have an option to not generate this port so in the sblock design the module will look nicer.5 votes -
Add register input/output pipeline option using generic
Hello,
In order to help timing closure, it would be extremely helpful to add an option to insert extra register for input/outputs.
I suggest that each register (or array) would have a generic associated with the number of extra register pipeline we want to insert :GREG1OUTEXTRAPIPE := 0; -- no extra pipeline
GREG1INEXTRAPIPE := 0; -- no extra pipeline
GREG2OUTEXTRAPIPE := 1; -- 1 register per REG1 out field added
GREG2INEXTRAPIPE := 2; -- 4 register per REG2 in field addedThis will…
4 votesHi Guillaume, thanks for suggesting this. We'll be looking into it.
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uvmreg generation
generate uvm register format
4 votesHi, thanks for suggesting this feature. Could you please send us an example of how file should look like?
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Generate RTF/Microsoft Word Documentation
The RTF format should make it easier to import register tables into Microsoft Word.
4 votes -
Optional "accept" for write/read
Currently, user logic can not stall the register file, as soon as a read/write happens, the strobe will go high and one cycle later go low. If the user logic is not ready to take in/provide a value, the value might be lost. I think it would be nice to have an optional flag to have a handshake like AXI:
During a read, the strobe would go high, the statemachine would go into a READWAITREADY state, where the strobe is held high until ready is asserted from user logic. Only once that happens, the statemachine goes into READ_RESPONSE…3 votesThanks for suggesting this feature. For further analysis, it would be very helpful if you could provide a concrete application example for this. Thanks, Guy.
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Add functions for setting/getting register field values
When writing testbenches, we often have to set/get the value of single fields within a variable representing the value of a register.
Currently, the only way to do that is to use the <register><field>BITOFFSET and <register><field>BITWIDTH from the VHDL/SV packages:
MemRegv(CTRLDURATIONBITWIDTH + CTRLDURATIONBITOFFSET - 1 downto CTRLDURATIONBITOFFSET) := "1000";
I would be nice to have a "setregisterfield" function for that, which could take the register and field names as arguments:
MemRegv := setregisterfield("CTRL", "DURATION", "1000", MemRegv);
2 votes -
Type cast registers
Ability to type cast registers i.e. signed or unsigned rather than stdlogicvector to be more descriptive.
2 votesThanks for the feedback!
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Support for IPXACT readAction
This is information about the register behaviour when read. A common special behaviour is "Clear on read" which is often used in Interrupt Status Registers.
2 votes
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